Motivation:

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1. Help understand transistor level circuits of competitors’ products

2. Generate evidence for license negotiations or litigation cases

3. Extract layout rules, schematics to facilitate product transfer from one wafer foundry to another.

4. Understand the transistor level circuit to resolve quality issues

 

​LTEC has unique capabilities to extract the transistor level circuit diagram down to 14nm process node, including product sourcing, node profile analysis, design rule analysis, cell library analysis, simulation as well as cost analysis.

Deliverables are PDF format report and EDIF data. The cross reference viewer is also available.

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Example：

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Circuit analysis of Multicell Battery Monitors LSI for Automotive (HV,EV,PHV Cars)

0.6um BCMOS process (3- Metal/2-poly-Si)

 

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